The present invention relates to the offset compensation of operational amplifiers. More particularly, the present invention concerns an offset compensation for use in display drivers for liquid crystal displays.
Various approaches are known for the compensation of the offset at the output of operational amplifiers (OpAmps). Two basic approaches for the offset compensation can be distinguished.
The first approach uses a capacitor in order to store the offset. A corresponding block diagram is given in FIG. 1. The circuitry of FIG. 1 works as follows. A series of pulses is applied to the switches S1 and S2 in order to switch the circuit arrangement from a first phase (1) to a second phase (2) and vice versa. The respective lines are not illustrated in FIG. 1. In the phase (1), the switches S1 are closed and the operational amplifier 10 is operated in a unity gain loop where the output voltage at the output 12 of the operational amplifier 10 is equal to the offset voltage (Voff).
During phase (1) the voltage (Voff) at the output 12 is stored in the capacitor 13 (Coff). During phase (2), the switches S1 are open and the switch S2 is closed. The capacitor 13 is thus put in series with the negative input 14 of the operational amplifier 10. Since the offset voltage (Voff) is stored in the capacitor 13 (Coff), the negative and the positive input of the operational amplifier 10 both are at the same potential. As a consequence, the voltage at the output 12 of the operational amplifier 10 is cancelled, provided that the voltage difference between the inputs 15 and 16 is zero too.
An example of such a system is described in U.S. Pat. No. 4,781,437.
It is a typical disadvantage of this first approach that the offset cancellation is degraded by the charge injection caused by the auto-zero switches S1 and S2.
A typical example of a circuit according to the second approach is illustrated in FIG. 2. In this case, a supplementary gain stage 21 is employed. This gain stage 21 provides for a compensation of the offset at the output side of the operational amplifier 20 rather than at the input side. Circuits according to the second approach are also switched from a first phase (1) to a second phase (2) by applying a series of pulses to the switches S1 and S2. During phase (1), the switches S1 are closed and the inputs 24, 25 of the operational amplifier 20 (amplification A1) are connected (shorted together) and the operational amplifier 22 (amplification A2) of the gain stage 21 is operated in a closed loop. The closed loop forces the output 26 of the operational amplifier 23 to a point in the linear region. In phase (2) when the switch S1 on the capacitor 27 opens, the charge that was injected therein yields a supplementary offset voltage. This supplementary offset voltage is amplified by the factor A2 and appears at the output 26. The offset at the output 28 of the operational amplifier 20 is thus compensated.
The two approaches discussed in the preceding sections correct the offset in two phases (1) and (2), which have usually the same length. In other words, these approaches have a duty cycle of about 50%.
In order to be able to obtain a higher duty cycle (up to 100%), a so-called ping pong topology is employed, in which a load at the output side of the operational amplifier can be always driven. This is achieved by adding more stages in parallel and using them in a xe2x80x9cmultiplexedxe2x80x9d way. While one stage compensates the offset, the other one drives the load.
There are applications where a high duty cycle is requested and the time available for the offset correction, during the different phases, can be smaller than the settling time of the whole system. The ping pong approach could theoretically solve this problem, but it implies the doubling (or more) of the circuitry and hence of the silicon chip area.
In applications where hundreds of such circuits are present on the same die, a different solution is needed to obtain a device with a competitive price and silicon area.
It is another disadvantage of known solutions that the transient from the offset correction phase (1) to the active phase (2) is too long.
It is an object of the present invention to provide a scheme that overcomes the disadvantages of know approaches that are either slow or require extra silicon area on the die.
It is a further object of the present invention to provide a scheme that allows for a better offset compensation or even an offset cancellation.
It is another object of the present invention to provide a scheme that allows for an offset compensation in display drivers, and in particular in LCD display drivers.
The present invention concerns a scheme that allows the output voltage of an amplifier circuit arrangement to be compensated for variations in the offset voltage of the amplifier.
These and other objects are achieved by a circuit arrangement that comprises an input amplifier stage with two inputs and an output being connectable to an input of an output amplifier stage. The circuit arrangement also comprises a comparator with a first input, a second input and a comparator output, a feedback capacitor connected to an offset tuning input of the input amplifier stage, and a plurality of switches that are controllable by switching signals. These signals allow the circuit arrangement to be switched from a first phase (1) to a second phase (2). During the first phase, the output of the input amplifier stage and the input of the output amplifier stage are separated by one of the switches, the two inputs of the input amplifier stage are connected via another switch, the first input of the comparator is connected to the output of the input amplifier stage and the second input of the comparator is connected to the input of the output amplifier stage such that via the comparator output a charge on the feedback capacitor and hence the voltage at the offset tuning input is altered. An offset of the input amplifier stage is thus corrected.
Further advantageous implementations are claimed in the claims 2-16.
Also provided is a display system that comprises a display screen with a plurality of source lines and gate lines, a gate driver, and a source driver module, the display system receiving input signals representing the information that is to be displayed on the display screen. The source driver module comprises a buffer with a circuit arrangement in accordance with the present invention.
Further advantageous implementations of a display system in accordance with the present invention are claimed in the claims 18-19.
The method according to the present invention allows to compensate the offset voltage of an input amplifier stage with two inputs and an output. The input amplifier stage is part of a circuit arrangement that comprises an output amplifier stage with an input that is connectable to the output of the input amplifier stage, a comparator with a first input, a second input and a comparator output, a feedback capacitor connected to an offset tuning input of the input amplifier stage, and several switches. In accordance with the present invention, the following steps are performed in order to compensate the offset voltage of an input amplifier stage:
closing first switches and opening second switches,
sensing a voltage difference between the first input and the second input of the comparator in order to generate an output current at the comparator output,
charging or discharging the feedback capacitor using the output current,
adjusting the offset of the input amplifier stage via the offset tuning input.
Various advantageous implementations and variations of the method are claimed in the claims 21-31.